At present, in 3GPP (3rd Generation Partnership Project), standardization is in progress with respect to a W-CDMA (Wideband-Code Division Multiple Access) technique that is one of third-generation mobile communication systems. Moreover, as one theme for the standardization, there is specified an HSDPA (High Speed Downlink Packet Access) system that provides a high-speed packet transfer of maximum approx. 14 Mbps in a downlink.
The HSDPA employs an adaptive coding modulation technique, and, for example, is characterized in that switching between a QPSK (Quadrature Phase Shift Keying) modulation technique and a 16 QAM (16 Quardrature Amplitude Modulation) technique is made in accordance with radio environments between a base station and a mobile station. Moreover, the HSDPA employs an HARQ (Hybrid Automatic Repeat reQuest) technique.
The HSDPA is characterized in that, when a mobile station has detected an error with respect to reception data from a base station, the data is retransmitted from the base station in response to a request from the mobile station and the mobile station carries out error correction decoding by employing both the already received data and the retransmitted reception data. Thus, the HARQ effectively utilizes the already received data even if an error exists, thereby enhancing a gain of the error correction decoding and suppressing an increase in the number of times of retransmission.
As a principal transport channel for use in the HSDPA, there exists HS-DSCH (High Speed-Downlink Shared Channel). In the HS-DSCH, a data arrives at a coding unit as at most one transport block TTI (Transmission Time Interval) by TTI. As a process of coding the HS-DSCH, there exist CRC (Cyclic Redundancy Check) addition, turbo coding, HARQ, modulation (16 QAM/QPSK), etc (for example, see Non-patent document 1).
The conventional (3GPP-Standard) output device of the turbo encoder as mentioned above includes two constituent encoders (1st constituent encoder 100 and 2nd constituent encoder 200) as shown in FIG. 4. Herein, the 1st constituent encoder 100 is configured of a switch 101, operators (adders) 102 to 105, and delay circuits (D) 106 to 108, and 2nd constituent encoder 200 is configured of a switch 201, operators (adders) 202 to 205, and delay circuits (D) 206 to 208.
One constituent encoder (the 1st constituent encoder 100) directly inputs a data coding sequence Xk, whereas the other constituent encoder (the 2nd constituent encoder 200) inputs a sequence (a data coding sequence X′k) mixed with the data coding sequence by an interleaver (Turbo Code internal interleaver) 300.
Specifically, the data coding sequence (Systematic Bits) Xk is redundant data sequences Zk and Z′k that are output by two constituent encoders (the 1st constituent encoder 100 and the 2nd constituent encoder 200), respectively. Information X′k obtained by performing an interleaving process for the data coding sequence Xk is not outputted. The reason is that if a decoding side can decode the data coding sequence Xk, performing the interleaving process therefor makes it possible to obtain the information X′k for which the interleaving process has been performed.
A tail bit is an end bit for setting the bit held by each constituent encoder (the 1st constituent encoder 100 and the 2nd constituent encoder 200) back to zero after finishing the coding of the data sequence. A rate of the turbo Code is ⅓, and the output order is an order of X1, Z1, Z′1, X2, Z2, Z′2, . . . , Xn, Zn, and Z′n [where n=a code block size of the turbo coding], However, with normal coding of the data sequence, three kinds of codes are outputted, whereas, with coding of the tail bit, four kinds of codes are outputted. That is, according to a route of a signal line shown by dotted lines of FIG. 4, Xn+1, Zn+1, Xn+2, Zn+2, Xn+3, Zn+3, X′n+1, Z′n+1, X′n+2, Z′n+2, X′n+3, and Z′n+3 are outputted in this order.
In bit separation of the HRAQ, the turbo-coded data sequence, as shown in FIG. 5, lines up in an order of a 1st data coding bit (1st Systematic bit), a 1st Parity 1 bit, a 1st Parity 2 bit, a 2nd Parity 1 bit, a 2nd Parity 2 bit, a 3rd data coding sequence (3rd Systematic bit), . . . , a tail bit, so a bit separation unit 400 sequentially separates them into three sequences of
a 1st sequence 401: (all Systematic bits)+(some tail bits of Systematic & Parity 1 & Parity 2),
a 2nd sequence 402: (all Parity 1 bits)+(some tail bits of Systematic & Parity 1 & Parity 2), and
a 3rd sequence 403: (all Parity 2 bits)+(some tail bits of Systematic & Parity 1 & Parity 2).
The HARQ process is for causing the output bit number of the turbo code to match with a total bit number of a physical channel that is mapped to the HS-DSCH.
A Hybrid ARQ functionality, as shown in FIG. 6, is configured of two rate-matching stages (a 1st rate matching 620 and a 2nd rate matching 640) and one virtual buffer (virtual IR buffer 630).
Further, the 1st rate matching 620 includes a rate matching (RM_P1_1) 621 and a rate matching (RM_P2_1) 622, and the 2nd rate matching 640 includes a rate matching (RM_S) 641 and a rate matching (RM_P1_2) 642, and a rate matching (RM_P2_2) 643.
The 1st rate matching 620 (1st rate matching stage) causes the input bit number to match with the number of the bits (which are given by a higher layer) of the virtual IR buffer 630. However, when the input bit number does not exceed a capacity (bit number) of the virtual IR buffer 630, no process is performed for the data even though this 1st rate matching 620 is transparent hereto.
The 2nd rate matching 640 (2nd rate matching stage) causes the number of the bits subsequent to the process of the 1st rate matching 620 to match with a physical channel bit number at its TTI.
The 1st rate matching 620 of the HARQ, when the input bit number exceeds a capacity (bit number) of the virtual IR buffer 630, removes bits that are located at an appropriate position in sequences of the Parity 1 (2nd Sequence) and the Parity 2 (3rd Sequence). The removal position is decided with computation using a rate matching parameter. The data coding sequence (1st Sequence), which is not punctured, is directly inputted into the virtual IR buffer 630. The so-called puncturing process is a process of extracting the bit from the bit sequence at a constant period.
Next, how to calculate the 1st rate matching parameter in accordance with the conventional method will be explained.                (1) When NIR<NTTI, the number of bits that should be puncturedΔNilTTI=NIR−NTTI  [Numerical equation 1]is computed. Where, NTTI is a total number of the bits that are inputted from the turbo encoder.        
(2) Set a=2 when b=2;
a=1 when b=3
In a case of puncturing the Parity 1 bit, it follows that b=2.
In a case of puncturing the Parity 2 bit, it follows that b=3.
(3) Set
                              Δ          ⁢                                          ⁢                      N            i                          =                  {                                                                                          ⌊                                          Δ                      ⁢                                                                                          ⁢                                                                        N                          il                          TTI                                                /                        2                                                              ⌋                                    ,                                      b                    =                    2                                                                                                                                            ⌈                                          Δ                      ⁢                                                                                          ⁢                                                                        N                          il                          TTI                                                /                        2                                                              ⌉                                    ,                                      b                    =                    3                                                                                }                                    [                  Numerical          ⁢                                          ⁢          equation          ⁢                                          ⁢          2                ]            where,A function ┌y┐: an integral value is obtained, that is, y≦┌y┐<y+1A function └y┘: an integral value is obtained, that is, y−1<└y┘≦y  [Numerical equation 3]
(4) Computation of the rate matching parameterKi=NTTI/3eini=Ki eplus=α×Ki eminus=α×|ΔNi|
One example of the 1st rate matching process of the HARQ that is performed for the output of the turbo encoder shown in FIG. 4 is shown in FIG. 7. In this example, the process of the 1st rate matching of the HARQ process at the time that the bit number NTTI subsequent to the channel coding is 1500 and the number NIR of the bits allocated to the virtual IR buffer 630 is 1200 is exemplified.
In HARQ bit separation, the turbo-coded data is separated into three sequences of a data coding sequence (Systematic), a Parity 1 sequence (1st parity), and a Parity 2 sequence (2nd parity). Each of the data coding sequence, the Parity 1 sequence, and the Parity 2 sequence is configured of 496-bit code information and 4-bit tail bit information. The 4-bit tail bit information of each sequence has one part of the data coding sequence and each tail bit of the Parity 1 sequence and the Parity 2 sequence mixed.
Next, in the HARQ 1st rate matching, the rate matching with the capacity NIR=1500 of the virtual IR buffer 630 is carried out (it is only the parity bit that is punctured).
Upon computing the 1st rate matching parameter in accordance with the conventional,ΔNilTTI=1200−1500=−300  [Numerical equation 4]Ki=1500/3=500
The rate matching parameter of the Parity 1 is as follows.eini=500eplus=2×500=1000eminus=2×|ΔNi|=2×150=300
And, the rate matching parameter of the Parity 2 is as follows.eini=500eplus=500eminus=|ΔNi|=150
Non-patent document: “Multiple and channel coding 4.2.3.2 Turbo coding” [3GPP TS 25.212 V7.0.0 (2006-03) p. 16-21]